1. Field of the Invention
The present invention relates to management of the number of write/erase times in a nonvolatile semiconductor memory, and is used especially in a NAND-type flash memory.
2. Description of the Related Art
In recent years, a flash memory card in which a NAND-type flash memory is used has been used as storage mediums such as various portable information terminal including a digital camera. FIGS. 1 and 2 show outlines of a memory cell arrangement of the NAND-type flash memory.
A memory cell array of the NAND-type flash memory is constituted of a set of basic units, referred to as a NAND unit NU. The NAND unit NU is constituted of a cell row including a plurality of series-connected memory cells M0, M1, . . . M31, and two select gate transistors ST1, ST2 which are connected to opposite ends of the cell row.
In the NAND unit NU, two memory cells disposed adjacent to each other share one source/drain region. Moreover, the select gate transistor ST1 is connected to a bit line BL, and the select gate transistor ST2 is connected to a source line SL.
The memory cell array is divided by a unit of page or block. The page means the set of the memory cells connected to one word line. The page is a basic unit in performing operations such as write, erase, read. The block means a set of pages held between the select gate transistor ST1 on a bit line side and the select gate transistor ST2 on a source line side.
According to an example of FIG. 1, the memory cell array is constituted of X+1 blocks, and one block is constituted of 32 pages. A data length of one page is 528 bytes. Among these bytes, 512 bytes correspond to a data area which can freely be used by a user (user data portion), and the remaining 16 bytes correspond to a redundancy area. In general, in the redundancy area, an error correction circuit (ECC) code for error correction with respect to the data area, logical address, flag indicating whether the block is right or wrong, and the like are stored.
In this NAND-type flash memory, usually, data is erased by the unit of block (block erase). In this case, in data write/erase by a unit smaller than the block, that is, by the unit of page, cell data in the block including the page which is an object of write/erase is temporarily saved into a data storage portion such as another block, and the cell data of the page which is not the object of write/erase has to be protected.
Therefore, in enhancement of a write/erase function of the NAND-type flash memory, there are problems that this save operation requires much time.
To solve the problem, in recent years, a NAND-type flash memory has been developed in which the data can be erased by the page unit (e.g., see Documents 1, 2, 3).
Document 1: Jpn. Pat. Appln. KOKAI Publication No. 3-295097
Document 2: Jpn. Pat. Appln. KOKAI Publication No. 8-143398
Document 3: Jpn. Pat. Appln. KOKAI Publication No. 11-176177
In data erase (page erase) by the page unit, in one selected block, only the cell data of the page which is the object of write/erase may be erased. Therefore, it is not necessary to save the cell data of the page which is not the object of write/erase into another data storage portion.
However, the NAND-type flash memory including a page erase function has the following problem in reliability.
A write/erase operation is repeatedly performed only with respect to one specific page in one selected block. In this case, a voltage stress (intermediate voltage) is repeatedly applied to the memory cell of the page which is not the object of write/erase.
For example, every time data write is executed, the intermediate voltage smaller than a write voltage is applied to the memory cell of the page which is not the object of write/erase.
As a result, a threshold state of the memory cell of the page which is not the object of write/erase in one selected block gradually fluctuates. This finally results in destruction of the cell data. From this, it has heretofore been difficult to use the page erase function, for example, so as to increase a write/erase rate of file data.
As described above, a technique effective for realizing the enhancement of the write/erase function of the nonvolatile semiconductor memory has not heretofore existed.
Therefore, there has been a demand for development of a nonvolatile semiconductor memory in which the page erase function can be used to enhance the write/erase function of the data and which can avoid problems caused by the voltage stress applied to the memory cell of the page not forming the object of write/erase.